? 2000 fairchild semiconductor corporation ds009816 www.fairchildsemi.com october 1988 revised march 2000 dm96ls02 dual retriggerable resettable monostable multivibrator dm96ls02 dual retriggerable resettable monostable multivibrator general description the dm96ls02 is a dual retriggerable and resettable monostable multivibrator. the one-shot provides excep- tionally wide delay range, pulse width stability, predictable accuracy and immunity to noise. the pulse width is set by an external resistor and capacitor. resistor values up to 1.0 m w reduce required capacitor values. hysteresis is pro- vided on both trigger inputs of the dm96ls02 for increased noise immunity. features n required timing capacitance reduced by factors of 10 to 100 over conventional designs n broad timing resistor range1.0 k w to 2.0 m w n output pulse width is variable over a 2000:1 range by resistor control n propagation delay of 35 ns n 0.3v hysteresis on trigger inputs n output pulse width independent of duty cycle n 35 ns to output pulse width range ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. logic symbol v cc = pin 16 gnd = pin 8 pin descriptions connection diagram order number package number package description dm96ls02m m16a 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow dm96ls02n n16e 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide pin names description i 0 trigger input (active falling edge) i 0 schmitt trigger input (active falling edge) i1 schmitt trigger input (active rising edge) c d direct clear input (active low) q true pulse output q complementary pulse output
www.fairchildsemi.com 2 dm96ls02 functional description the dm96ls02 dual retriggerable resettable monostable multivibrator has two dc coupled trigger inputs per func- tion, one active low (i 0) and one active high (i1). the i1 input and i 0 input of the dm96ls02 utilize an internal schmitt trigger with hysteresis of 0.3v to provide increased noise immunity. the use of active high and low inputs allows either rising or falling edge triggering and optional non-retriggerable operation. the inputs are dc coupled making triggering independent of input transition times. when input conditions for triggering are met, the q output goes high and the external capacitor is rapidly discharged and then allowed to recharge. an input trigger which occurs during the timing cycle will retrigger the circuit and result in q remaining high. the output pulse may be terminated (q to the low state) at any time by setting the direct clear input low. retriggering may be inhibited by tying the q output to i 0 or the q output to i1. differential sensing tech- niques are used to obtain excellent stability over tempera- ture and power supply variations and a feedback darlington capacitor discharge circuit minimizes pulse width variation from unit to unit. schottky ttl output stages provide high switching speeds and output compatibility with all ttl logic families. logic diagram operation notes timing 1. an external resistor (r x ) and an external capacitor (c x ) are required as shown in the logic diagram. the value of r x may vary from 1.0 k w to 1.0 m w . 2. the value of c x may vary from 0 to any necessary value available. if, however, the capacitor has significant leakage relative to v cc /r x the timing equations may not represent the pulse width obtained. 3. the output pulse width t w for r x 3 10 k w and c x 3 1000 pf is determined as follows: t w = 0.43 r x c x where r x is in k w , c x is in pf, t is in ns or r x is in k w , c x is in m f, t is in ms. 4. the output pulse width for r x < 10 k w or c x < 1000 pf should be determined from pulse width versus c x or r x graphs. 5. to obtain variable pulse width by remote trimming, the following circuit is recommended: 6. under any operating condition, c x and r x (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. 7. v cc and ground wiring should conform to good high fre- quency standards so that switching transients on v cc and ground leads do not cause interaction between one shots. use of a 0.01 m f to 0.1 m f bypass capacitor between v cc and ground located near the circuit is recommended. triggering 1. the minimum negative pulse width into i 0 is 8.0 ns; the minimum positive pulse width into i1 is 12 ns. 2. input signals to the dm96ls02 exhibiting slow or noisy transitions can use either trigger as both are schmitt trig- gers. 3. when non-retriggerable operation is required, i.e., when input triggers are to be ignored during quasi-stable state, input latching is used to inhibit retriggering. 4. an overriding active low level direct clear is provided on each multivibrator. by applying a low to the clear, any timing cycle can be terminated or any new cycle inhibited until the low reset input is removed. trigger inputs will not produce spikes in the output when the reset is held low. a low-to-high transition on c d will not trigger the dm96ls02. if the c d input goes high coincident with a trigger transition, the circuit will respond to the trigger.
3 www.fairchildsemi.com dm96ls02 operation notes (continued) triggering truth table h = high voltage level 3 v ih l = low voltage level v il x = immaterial (either h or l) h ? l = high-to-low voltage level transition l ? h = low-to-high voltage level transition typical performance characteristics output t w vs. r x and c x i1 delay time vs. t a i 0 delay time vs. t a output t w vs. t a pin numbers operation 5(11) 4(12) 3(13) h ? l l h trigger hl ? hhtrigger x x l reset
www.fairchildsemi.com 4 dm96ls02 typical performance characteristics (continued) normalized d t w vs. t a pulse width vs. r x c x input pulse f @ 100 khz amp @ 3.0v width @ 100 ns t r = t f 5 ns figure 1.
5 www.fairchildsemi.com dm96ls02 absolute maximum ratings (note 1) note 1: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the recommended operating conditions table will define the conditions for actual device operation. recommended operating conditions electrical characteristics over recommended operating free air temperature range (unless otherwise noted) note 2: all typicals are at v cc = 5v, t a = 25 c. note 3: not more than one output should be shorted at a time, and the duration should not exceed one second. supply voltage 7v input voltage 7v operating free air temperature range 0 c to + 70 c storage temperature range - 65 c to + 150 c symbol parameter min nom max units v cc supply voltage 4.75 5 5.25 v v ih high level input voltage 2 v v il low level input voltage 0.8 v i oh high level output current - 0.4 ma i ol low level output current 8 ma t a free air operating temperature 0 70 c symbol parameter conditions min typ max units (note 2) v i input clamp voltage v cc = min, i i = - 18 ma - 1.5 v v oh high level v cc = min, i oh = max, 2.7 3.4 v output voltage v il = max v ol low level v cc = min, i ol = max, 0.35 0.5 output voltage v ih = min v i ol = 4 ma, v cc = min 0.25 0.4 i i input current @ max v cc = max, v i = 7v 0.1 ma input voltage v i = 10v i ih high level input current v cc = max, v i = 2.7v 20 m a i il low level input current v cc = max, v i = 0.4v - 0.4 ma i os short circuit output current v cc = max (note 3) - 20 - 100 ma i cc supply current v cc = max 36 ma v t + positive-going threshold 2.0 v voltage, i 0, i1 v t - negative-going threshold 0.8 v voltage, i 0, i1
www.fairchildsemi.com 6 dm96ls02 switching characteristics v cc = + 5.0v, t a = + 25 c note 4: applies only over commercial v cc and t a range for 96s02. symbol parameter c l = 15 pf units min max t plh propagation delay 55 ns i0 to q t phl propagation delay 50 ns i0 to q t plh propagation delay 60 ns i1 to q t phl propagation delay 55 ns i1 to q t phl propagation delay 30 ns c d to q t plh propagation delay 35 ns c d to q t w (l) i0 pulse width low 15 ns t w (h) i1 pulse with high 30 ns t w (l) c d pulse width low 22 ns t w (h) minimum q pulse width high 25 55 ns t w q pulse width 4.1 4.5 m s r x timing resistor range (note 4) 1 1000 k w t change in q pulse 1.0 % width over temperature t change in q pulse 0.8 % width over v cc range 1.5
7 www.fairchildsemi.com dm96ls02 physical dimensions inches (millimeters) unless otherwise noted 16-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow package number m16a
www.fairchildsemi.com 8 dm96ls02 dual retriggerable resettable monostable multivibrator physical dimensions inches (millimeters) unless otherwise noted (continued) 16-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300 wide package number n16e fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
